Staff Digital Verification Engineer - Lead Role

Verification of mixed-signal ASICs in a SV UVM environment. Implementing test cases based on functional specifications and test plans. RTL and possibly Gate level debug of mixed-signal ASICs. Implementing functional coverage and aiding designers in...

• Date Posted:

  5/28/2024 

• Remote Work Level:

  100% Remote

• Location:

  Canada

  

• Job Type:

  Employee

• Job Schedule:

  Full-Time

• Career Level:

  Experienced

• Travel Required:

  No specification

• Categories:

  Computer & IT, Engineering, Python

• Company:

  Company details here

• Benefits:

  Company Benefits here

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